1. Field of the Invention
The present invention relates to a D-type latch circuit and a D-type flip-flop circuit that are composed of MOS field effect transistors.
2. Description of the Related Art
FIG. 6 illustrates a configuration of a conventional dynamic D-type flip-flop circuit 30.
The dynamic D-type flip-flop circuit 30 includes a master latch 31 and a slave latch 32. The master latch 31 includes a transfer gate 23 and an inverter 24. The slave latch 32 includes a transfer gate 25 and an inverter 26.
FIG. 7 illustrates a configuration of the transfer gates 23 and 25 shown in FIG. 6. The transfer gate shown in FIG. 7 includes a p-channel MOS field effect transistor 27 (hereinafter referred to as P-MOS transistor) and an n-channel MOS field effect transistor 28 (hereinafter referred to as N-MOS transistor). The source and drain of the P-MOS transistor 27 are connected to the source and drain of the N-MOS transistor 28.
Referring to FIG. 7, when an input signal S is at a high level (hereinafter referred to as H level), an inverse input signal -S of the input signal S is at a low level (hereinafter referred to as L level). In this case, the P-MOS transistor 27 and the N-MOS transistor 28 are in the open state, and thus a signal A input to the transfer gate is output as a signal Y from the transfer gate.
When the input signal S is at the L level, the inverse input signal -S is at the high level. In this case, the P-MOS transistor 27 and the N-MOS transistor 28 are in the closed state, and thus the signal A input to the transfer gate is not output from the transfer gate.
FIG. 8 illustrates a configuration of an inverter. The inverter shown in FIG. 8 includes a P-MOS transistor 29 and an N-MOS transistor 30. The gate of the P-MOS transistor 29 is connected to the gate of the N-MOS transistor 30. The source of the P-MOS transistor 29 is connected to a power source V.sub.DD. The source of the N-MOS transistor 30 is connected to a ground GND. The drain of the P-MOS transistor 29 is connected to the drain of the N-MOS transistor 30.
The dynamic D-type flip-flop circuit 30 shown in FIG. 6 receives clock signals BCK and -BCK. FIG. 9 illustrates a clock generating circuit for generating the clock signals BCK and -BCK. The clock generating circuit shown in FIG. 9 includes inverters 51 and 52. The clock generating circuit shown in FIG. 9 generates the clock signals BCK and -BCK from a clock signal CK.
FIG. 10 illustrates a configuration of a conventional static D-type flip-flop circuit 60. The static D-type flip-flop circuit 60 includes a master latch 61 and a slave latch 62. The master latch 61 includes transfer gates 35 and 38, and inverters 36 and 37. The slave latch 62 includes transfer gates 39 and 42, and Inverters 40 and 41. The transfer gates 35, 38, 39, and 42 have the same configuration as that shown in FIG. 7.
The conventional static D-type flip-flop circuit 60 is the same operation as that of the dynamic D-type flip-flop circuit 30 shown in FIG. 6. However, for example, when the transfer gate 35 of the static D-type flip-flop circuit 60 is in the closed state, the transfer gate 38 is in the open state while holding a signal, which has been input to the transfer gate 35 in the immediately previous open state, in a circuit of the transfer gate 38 and the inverters 36 and 37. Therefore, even when the transfer gate 35 is in the closed state, the signal which has been input to the transfer gate 35 in the immediately previous open state is output from the master latch 61. The same applies to the slave latch 62.
The conventional flip-flop circuits 30 and 60 require the clock signals BCK and -BCK having reversed polarities. In order to obtain the clock signals BCK and -BCK using the clock signal CK, the clock generating circuit shown in FIG. 9, i.e., the inverter, is necessary.